1. Field of the Invention
The present invention relates to a protection circuit. In particular, the present invention relates to a protection circuit including a thyristor formed on a semiconductor substrate, and to a protection circuit provided between a first terminal and a second terminal to provide protection against an overvoltage and an overcurrent caused by electrostatic discharge (ESD) or the like.
2. Description of Related Art
Up to now, in the field of semiconductor integrated circuit, various types of protection circuits including a diode, a MOS transistor, or the like are used to prevent an input/output terminal and a power supply terminal from being destroyed by static electricity. In particular, with the recent trend toward miniaturization and higher integration of semiconductor integrated circuits, semiconductor devices are more easily destroyed by static electricity. For this reason, the importance of protection circuits against static electricity has been increasing, and the research and development on protection circuits has been vigorously conducted by various manufacturers. Of the protection circuits, a thyristor (SCR) type protection circuit has been attracting attention recently, because of its excellent discharge capacity.
For example, Japanese Unexamined Patent Application Publication No. 2005-101485 (see FIG. 24) filed by the present inventor discloses a thyristor-type protection circuit in which a trigger element is connected between an N-well tap and a P-well tap so as to trigger a PNP transistor and an NPN transistor, which constitute a thyristor, at substantially the same time, thereby rapidly providing protection against static electricity FIG. 28 shows a circuit diagram of the protection circuit, and FIG. 29 is a cross-sectional view showing the configuration of the protection circuit.
Further, “Implementation of Diode and Bipolar triggered SCRs for CDM Robust ESD protection in 90 nm CMOS ASICs”; IBM, 2005 EOS/ESD Symposium (Ciaran J Brennan, Shunhua Chang, Min Woo, Kiran Chatty, Robert Gauthier) discloses a thyristor-type electrostatic protection circuit in which a dual base Darlington bipolar transistor is used as a trigger element in a CMOS device having a triple well structure so as to operate at high speed. FIG. 30 is a cross-sectional view showing the configuration of the circuit.
Furthermore, Japanese Unexamined Patent Application Publication No. 2000-277700 (see FIG. 6B) (Men Wan Riu et al.) discloses a circuit in which a primary protection device incorporating a thyristor and a secondary protection device incorporating an NMOS transistor are used in combination, and sources of the primary protection device and the secondary protection device are used in common so as to lower a trigger voltage for the primary protection device to a voltage close to a trigger voltage for the secondary protection device, to thereby effectively attain the protection. FIG. 31 is a cross-sectional view showing the configuration of the circuit.